Logic elements are basic modules of today's digital computers. Since these basic modules are often used in digital computers, an improvement of a basic module has the direct effect of improving the entire apparatus in which this basic module is used. Above all, the number of transistors required for the realization of the basic module, the power loss that is converted in the basic module, and the speed of this basic module, are particularly important for the efficiency and the quality of such a basic module. The use of standardized technology is also an essential factor in assessing the quality of such a basic module.
The realization of logical basic circuits based on their functional equation by resistance logic (RTL), by diode transistor logic (DTL), by slow noise-proof logic (LSL) and by transistor-transistor logic (TTL), by emitter-coupled logic (ECL), complementary MOS logic (CMOS) and by NMOS logic (see U. Tietze, Ch. Shenk, Halbleiterschaltungstechnik, .sub.9 th ed., Springer-Verlag, 1990, ISBN 3-540-19475-4, pp. 201-219), is known. The use of neuron MOS transistors for the realization of a binary full adder is also known (T. Shibata, T. Ohini: "A functional 1405 transistor featuring gate-level weighted sum and threshold operations," IEEE Transactions on Electron Devices, 39, pages 1444-1455, 1992). The disadvantages of these known circuit arrangements, are above all, that a larger number of transistors is required in comparison to the invention specified below. The speed of known circuit arrangements is also considerably less than that of the circuit arrangement of the invention. A considerable disadvantage of neuron MOS transistors is that a specific technology (EEPROM or analog process) has to be used.
From (J. A. Hidalgo-Lopez et al., New Types of Digital Comparators, IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 29-32, April 1995), a comparator circuit is known that comprises two regeneratively coupled inverter stages and a reset unit. Two electrical quantities to be compared are supplied to the outputs of the inverter stages, at which the comparison result is also present. The source terminals of both inverter stages are connected with one another, and are connected to the frame via a clock transistor.
From (D. Ferrari and R. Stefanelli, Some New Schemes for Parallel Multipliers, Alta Frequenza, vol. 38, no. 11, pp. 843 to 852, XP 0020141008, 1969), a basic structure of a multiplier cell on the system plane is known with two different units for the formation of an output carry bit, as well as of an output summation bit. Fundamentally, the use of resistor-transistor logic (RTL) is proposed. The two elements are connected with one another in such a way that an output signal of a first element is fed back to an input of the second element. The fed-back output signal is weighted differently at the input of the second element, than are all other input signals.
Basic principles of a neuron 1405 inverter are known from (T. Shibata et al., Neuron-MOS Binary Logic Integrated Circuits--Part 2: simplifying Techniques of Circuit Configuration and a Practical Applications [sic], IEEE Transactions on Electron Devices, vol. 40, no. 6, pp. 974-979, 1993).